W90N745CD/W90N745CDG
UART Interrupt Enable Register (UART_IER)
REGISTER OFFSET
R/W
DESCRIPTION
RESET VALUE
R/W
UART_IER
0x04
Interrupt Enable Register (DLAB = 0)
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
6
3
2
1
0
RESERVED
nDBGACK_EN
MSIE
RLSIE
THREIE
RDAIE
BITS
DESCRIPTIONS
Reserved
[31:5]
-
ICE debug mode acknowledge enable
0 = When DBGACK is high, the UART receiver time-out clock will
be held
nDBGACK_EN
[4]
1 = No matter what DBGACK is high or not, the UART receiver
timer-out clock will not be held
MODEM Status Interrupt (Irpt_MOS) Enable
0 = Mask off Irpt_MOS
1 = Enable Irpt_MOS
MSIE
[3]
[2]
Receive Line Status Interrupt (Irpt_RLS) Enable
0 = Mask off Irpt_RLS
RLSIE
1 = Enable Irpt_RLS
Transmit Holding Register Empty Interrupt (Irpt_THRE)
Enable
0 = Mask off Irpt_THRE
1 = Enable Irpt_THRE
THREIE
RDAIE
[1]
[0]
Receive Data Available Interrupt (Irpt_RDA) Enable and
Time-out Interrupt (Irpt_TOUT) Enable
0 = Mask off Irpt_RDA and Irpt_TOUT
1 = Enable Irpt_RDA and Irpt_TOUT
- 264 -
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