W90N745CD/W90N745CDG
31
23
15
7
30
22
14
6
29
21
28
Reserved
27
19
11
3
26
18
10
2
25
17
24
16
8
20
Reserved
PRS[3:0]
13
12
9
Reserved
5
4
1
0
BCLK_SEL[1:0]
FS_SEL
MCLK_SEL FORMAT
Reserved
BITS
DESCRIPTIONS
[31:20]
Reserved
-
I²S frequency pre-scaler selection bits. (FPLL is the input PLL
frequency, MCLK is the output main clock)
PSR[3:0]=0000, MCLK=FPLL/1
PSR[3:0]=0001, MCLK=FPLL/2
PSR[3:0]=0010, MCLK=FPLL/3
PSR[3:0]=0011, MCLK=FPLL/4
PSR[3:0]=0100, MCLK=FPLL/5
PSR[3:0]=0101, MCLK=FPLL/6
PSR[3:0]=0110, MCLK=FPLL/7
PSR[3:0]=0111, MCLK=FPLL/8
PSR[3:0]=1000, reserved
[19:16]
PRS[3:0]
PSR[3:0]=1001, MCLK=FPLL/10
PSR[3:0]=1010, reserved
PSR[3:0]=1011, MCLK=FPLL/12
PSR[3:0]=1100, reserved
PSR[3:0]=1101, MCLK=FPLL/14
PSR[3:0]=1110, reserved
PSR[3:0]=1111, MCLK=FPLL/16
(when the division factor is 3/5/7, the duty cycle of MCLK is not
50%, the high duration is 0.5*FPLL)
The PSR[3:0] bits are read/write
Publication Release Date: September 22, 2006
- 245 -
Revision A2
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