W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
32-bit play destination address length
[31:0]
AUDIO_PDST_L[31:0]
The AUDIO_PDST_L[31:0] bits is read/write.
DMA destination current address (ACTL_PDSTC)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF0_9020 RO
DMA play destination current address
0x0000_0000
ACTL_PDSTC
The value in ACTL_PDSTC is the DMA play destination current address, this register could only be
read by CPU.
31
23
15
7
30
22
14
6
29
21
13
5
28
AUDIO_PDSTC[31:24]
20 19
AUDIO_PDSTC[23:16]
12 11
AUDIO_PDSTC[15:8]
27
26
18
10
2
25
17
9
24
16
8
4
3
1
0
AUDIO_PDSTC[7:0]
BITS
DESCRIPTIONS
32-bit play destination current address
[31:0]
AUDIO_PDSTC[31:0]
The AUDIO_PDSTC[31:0] bits is read/write.
Audio controller playback status register (ACTL_PSR)
REGISTER
ACTL_PSR
ADDRESS
R/W
DESCRIPTION
RESET VALUE
Audio controller FIFO and DMA
status register for playback
0xFFF0_9024 R/W
0x0000_0004
Publication Release Date: September 22, 2006
Revision A2
- 243 -
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