W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.10 Register 9: ( Default : 25h )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
PCIF5 free running control
7
PCIF5_FR_N
0
1 : Stoppable with PCI_STOP# assertion
0 : Free running
R/W
LTE pin strap value
0 : allow over-clocking
1 : forbid over-clocking
6
5
4
LTE_RB
0
1
0
Latch
R/W
R/W
Reserved
TEST_SEL
Allow to select output status
0 : All outputs are tri-state
1 : All outputs are REF/N besides REF clock
Allow to entry test mode
0 : Normal operation
1 : Entry test mode
Programmable VDDXXX_IO
111 : 1.0V
3
TEST_ENTRY
0
R/W
R/W
2
1
0
IO_RAIL<2>
IO_RAIL<1>
IO_RAIL<0>
1
0
1
110 : 0.9V
101 : 0.8V
100 : 0.7V
others : 0.6V
7.11 Register 10: ( Default : D0h )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
NVAL<8>
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
Programmable N divisor value for CPU frequency.
Bit 7 ~0 are defined in the Register 11.
R/W
NVAL<9>
NVAL<10>
MVAL<4>
MVAL<3>
MVAL<2>
Programmable M divisor for CPU frequency.
Default value follow FS=2 (01_0000 = 16)
R/W
MVAL<1>
MVAL<0>
Publication Release Date: December, 2006
Revision 1.0
- 15 -
WINBOND [ WINBOND ]
