W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.5 Register 4: ( Default : FFh)
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
SRC3 output control
7
SRCEN<3>
SRCEN<2>
SRCEN<1>
SRCEN<0>
CPUEN<1>
CPUEN<0>
SS1_EN
1
R/W
1: Output enable
0: Output disable
SRC2 or SATA output control
1: Output enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0: Output disable
SRC1 output control
1: Output enable
0: Output disable
SRC0 or DOT96 output control
1: Output enable
0: Output disable
CPU1 output control
1: Output enable
0: Output disable
CPU0 output control
1: Output enable
0: Output disable
Spread spectrum enable for CPULOOP
1: Enable
0: Disable
Spread spectrum enable for PCIELOOP
1: Enable
SS3_EN
0: Disable
Publication Release Date: December, 2006
Revision 1.0
- 11 -
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