W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.6 Register 5: ( Default : 00h )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
Enable CR#_A (clock request) feature
1: Enable
=>configure PCI0/CR#_A as input pin, CR#_A.
7
CR#_A_EN
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
0
R/W
=>Set Reg2-Bit0 to 0, disable PCI0 clock output,
prior to activate this feature
0 : Disable
keep PCI0/CR#_A as output pin, PCI0.
Select SRC0 or SRC2 to be controlled by CR#_A.
1: SRC2
6
5
4
3
2
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
0: SRC0
Enable CR#_B (clock request) feature
1: Enable
=>configure PCI1/CR#_B as input pin, CR#_B.
=>Set Reg2-Bit1 to 0, disable PCI1 clock output,
prior to activate this feature
0 : Disable
keep PCI1/CR#_B as output pin, PCI1.
Select SRC1 or SRC4 to be controlled by CR#_B.
1: SRC4
0: SRC1
Enable CR#_C (clock request) feature
1: Enable
=>configure SRC3T/CR#_C as input pin, CR#_C.
=>Set Reg4-Bit7 to 0, disable SRC3 clock output,
prior to activate this feature
0 : Disable
keep SRC3T/CR#_C as output pin, SRC3T.
Select SRC2 or SRC0 to be controlled by CR#_C.
1: SRC2
0: SRC0
Enable CR#_D (clock request) feature
1: Enable
=>configure SRC3C/CR#_D as input pin, CR#_D.
1
0
CR#_D_EN
CR#_D_SEL
0
0
R/W
R/W
=>Set Reg4-Bit7 to 0, disable SRC3 clock output,
prior to activate this feature
0 : Disable,
Keep SRC3C/CR#_D as output pin,SRC3C.
Select SRC4 or SRC1 to be controlled by CR#_D.
1: SRC4
0: SRC1
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