W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.7 Register 6: ( Default : 0Ch )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
Enable CR#_E (clock request) feature for SRC6
1: Enable
=>configure SRC7C/CR#_E as input pin, CR#_E.
R/W
7
CR#_E_EN
CR#_F_EN
0
=>Set Reg3-Bit3 to 0, disable SRC7 clock output,
prior to activate this feature
0 : Disable
keep SRC7C/CR#_E as output pin, SRC7C.
Enable CR#_F (clock request) feature for SRC8
1: Enable
=>configure SRC7T/CR#_F as input pin, CR#_F.
6
0
R/W
R/W
R/W
=>Set Reg3-Bit3 to 0, disable SRC7 clock output,
prior to activate this feature
0 : Disable
keep SRC7T/CR#_F as output pin, SRC7C.
Enable CR#_G (clock request) feature for SRC9
1: Enable
=>configure SRC11C/CR#_G as input pin, CR#_G.
5
4
CR#_G_EN
CR#_H_EN
0
0
=>Set Reg3-Bit7 to 0, disable SRC11 clock output,
prior to activate this feature
0 : Disable, keep SRC11C/CR#_G as output pin,
SRC11C.
Enable CR#_H (clock request) feature for SRC10
1: Enable
=>configure SRC11T/CR#_H as input pin, CR#_H.
=>Set Reg3-Bit7 to 0, disable SRC11 clock output,
prior to activate this feature
0:Disable, keep SRC11T/CR#_H as output pin,
SRC11T.
3
2
Reserved
Reserved
1
1
R/W
R/W
SRC1 free running control
1 : Stoppable with PCI_STOP# assertion
0 : Free running
SRCs free running control
1 : Stoppable with PCI_STOP# assertion
0 : Free running
1
0
SRC1_FR_N
SRCs_FR_N
0
0
R/W
R/W
Publication Release Date: December, 2006
Revision 1.0
- 13 -
WINBOND [ WINBOND ]
