W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.15 Register 14: ( Default : 04h )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
7
6
Reserved
Reserved
0
0
R/W
R/W
Enable spread spectrum to SATA with –0.5%, only
valid in SRCs over-clocking mode.
1 : Enable
0 : Disable
5
SATA_SSC_EN
0
4
3
PCIEMN_EN
CPUMN_EN
0
0
Enable programming PCIE frequency
R/W
R/W
Enable programming CPU frequency
Software PCISTOP function
0 : Stop all STOPPABLE PCI,PCIF and SRC clock
2
SW_PCISTOP_N
1
with no glitches.
R/W
1 : Resume all STOPED PCI,PCIF and SRC clock
with no glitches.
Configure the input/output function of
SRC5T/PCISTOP_N and SRC5C/PCISTOP_N
Latch
R
1
0
SRC5_EN
FSD
0
0
1 : Output feature, SRC5.
0 : Input feature, PCISTOP_N & CPUSTOP_N.
Latch
R
Frequency table select bit.
7.16 Register 15: ( Default : 0Bh )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
7
6
5
4
3
2
1
0
SPH VAL1<3>
0
0
0
0
1
0
1
1
SPH VAL1<2>
SPH VAL1<1>
SPH VAL1<0>
SPL VAL1<3>
SPL VAL1<2>
SPL VAL1<1>
SPL VAL1<0>
Spread Spectrum Up Counter bit 3 ~ bit 0 for
CPULOOP .
R/W
Spread Spectrum Down Counter bit 3 ~ bit 0 for
CPULOOP.
2’s complement representation.
Ex: 1 -> 1111 ; 2 -> 1110 ; 7 -> 1001 ; 8 ->
1000
Publication Release Date: December, 2006
Revision 1.0
- 17 -
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