W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7.2 Register 1: ( Default : 83h)
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
Select SRC0 or DOT96
7
DOT96_SEL
1
R/W
0 : SRC0
1 : DOT96 (Default)
Down spread or center spread to total 0.5% for
CPULOOP
1: Center
0: Down
6
5
PLL1_SST_CEN_SEL
PLL3_SST_CEN_SEL
0
0
R/W
R/W
Down spread or center spread to total 0.5% for
PCIELOOP
1: Center
0: Down
4
3
2
1
PLL3_QCFB<3>
PLL3_QCFB<2>
PLL3_QCFB<1>
PLL3_QCFB<0>
0
0
0
1
PLL3 quick configuration bits <3:0>
See Table2. &
R/W
R/W
Set Reg0-bit3 = 1 prior to selecting these bits
except 0000 & 0001.
Sync PCI clock to CPU
0 : Async, PCI fix at 33.33M
1 : PCI follow SRC clocks
0
FIX_PCI_N
1
7.3 Register 2: ( Default : FFh )
AFFECTED PIN/
BIT
PWD
FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
REF output control
1: Output enable
0: Output disable
7
REFEN
1
R/W
USB48 output control
1: Output enable
6
5
4
USB48EN
PCIF5EN
PCIEN<4>
1
1
1
R/W
R/W
R/W
0: Output disable
PCIF5 output control
1: Output enable
0: Output disable
PCI4 output control
1: Output enable
0: Output disable
Publication Release Date: December, 2006
Revision 1.0
- 9 -
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