W83115RG-BW/W83115WG-BW
STEPLESS FOR INTEL BROADWATER CLOCK GENERATOR
7. I2C CONTROL AND STATUS REGISTERS
PWD: Power on default value
7.1 Register 0: ( Default : X1h )
AFFECTED PIN/
BIT
PWD
AFFECTED PIN / FUNCTION DESCRIPTION
TYPE
FUNCTION NAME(S)
7
6
5
FSC
X
X
X
FSB
FSA
Frequency table select bits.
Latch
0 : Legacy mode
1 : iMAT mode, Sticky 1
Set via SMBus or dynamically by combination of
4
IAMT_EN
0
R/W
PWRDWN, CPUSTOP_N and PCISTOP_N.
Sticky 1 : Mean that once written to a ‘1’ cannot be
cleared until power is removed.
Activate PCIELOOP
1 : Enable
3
2
1
PCIELOOP_EN
SRC_SYNC_N
FIX_SATA
0
0
0
R/W
R/W
R/W
0 : Disable
Sync SRC clock to CPU
1 : Async, SRC come from PCIELOOP
0 : Sync, SRC come from CPULOOP
Sync SATA clock to SRCs
1 : Async, SATA fix at 100M
0 : Sync, SATA follow SRC clocks
Save last configuration status in power down mode
1 : Save final configuration
0
PD_RESTORE
1
R/W
0 : Clear final configuration & return to power on
default.
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WINBOND [ WINBOND ]
