Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 11.1 Random Row Read (Interleaving Banks)
(Burst Length = 8, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK1
High
CS
RAS
CAS
WE
DSF
BS
RBy
RBy
RBx
RBx
RBx
RAx
A9
A0 ~ A8
CBx
CBy
CAx
tRCD
tAC1
tRP
DQM
DQ
Hi-Z
Bx6
Bx0
Ax1
Ax2
Ax4
Ax3 Ax5 Ax6
Bx3
Ax7
By0 By1
By2
Bx2
Bx7 Ax0
Bx1
Bx4
Bx5
Read
Precharge
Command
Bank A
Precharge
Activate
Activate
Command
Bank B
Command
Bank B
Command
Command
Bank A
Bank B
Read
Activate
Read
Command
Bank A
Command
Bank B
Command
Bank B
Document:
Rev.1
Page19