Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 11.2 Random Row Read (lnterleaving Banks)
(Burst Length = 8, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
DSF
BS
RBx
RBx
RBy
A9
RBx
A0 ~ A8
CBy
RAx
CAx
CBx
RBy
tAC2
tRP
tRCD
DQM
DQ
Hi-Z
Ax1
Ax0
Bx0
Bx3 Bx4
Activate
Bx7
Ax2 Ax4
Ax3
Ax7
By0
By1
Bx1 Bx2
Bx5 Bx6
Ax5
Ax6
Read
Precharge
Command
Bank B
Activate
Read
Command
Command
Bank B
Command
Bank A
Command
Bank B
Bank B
Activate
Read
Command
Command
Bank A
Bank B
Document:
Rev.1
Page20