Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Random Row Read (Interleaving Banks)
Figure 11.3
(Burst Length = 8, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
DSF
BS
RBx
RBx
RAx
RAx
RBy
RBy
A9
A0 ~ A8
CBy
CBx
CAx
tAC3
tRP
tRCD
DQM
DQ
Hi-Z
Ax5
Ax3 Ax4
Ax7
By0
Bx0
Ax1 Ax2
Ax0
Bx7
Ax6
Bx3
Bx5
Bx2
Bx4
Bx1
Bx6
Read
Precharge
Command
Bank A
Read
Activate
Read
Activate
Activate
Precharge
Command
Bank B
Command
Bank B
Command
Command
Bank B
Command
Command
Bank B
Command
Bank A
Bank B
Bank A
Document:
Rev.1
Page21