Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 10.3 Random Column Write (Page within same Bank)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
DSF
BS
RBw
A9
RBz
A0 ~ A8
RBw
CBy
CBz
CBx
RBz
CBw
DQM
DQ
Hi-Z
DBy2
DBy1
DBw1 DBw2
DBx1 DBy0
Write
DBy3
DBz0
DBz1 DBz2
DBw0
Write
DBx0
DBw3
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Write
Command
Bank B
Activate
Command
Command
Command
Bank B
Command
Bank B
Bank B
Bank B
Document:
Rev.1
Page18