Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Random Row Write (Interleaving Banks)
Figure 12.2
(Brust Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
DSF
BS
RAy
RAy
RAx
RAx
RBx
RBx
A9
A0 ~ A8
CAy
CAx
CBx
tRCD
tRP
tWR*
tWR*
DQM
DQ
Hi-Z
DBx7
DBx3
DBx5 DBx6
DAy2
DAy1
DAy4
DAy3
DAx5 DAx6
Activate
DBx4
DAy0
Write
DAx0
Write
DAx4
DAx3
DAx7 DBx0 DBx1
DAx2
DBx2
DAx1
Activate
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank A
Command
Bank A
Command
Bank B
Command
Bank A
Precharge
Command
Bank B
Precharge
Command
Bank A
* t
t
WR > WR(min.)
Document:
Rev.1
Page23
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
