Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 9.3 Random Column Read (Page within same Bank)
(Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
DSF
BS
RAz
RAz
RAw
RAw
A9
A0 ~ A8
CAy
CAx
CAw
CAz
DQM
DQ
Hi-Z
Az0
Aw1 Aw2 Aw3
Ax1
Ay2
Ax0
Ay3
Aw0
Ay0 Ay1
Activate
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Activate
Command
Command
Bank A
Command
Bank A
Bank A
Note: CKE to CLK disable/enable = 1 clock
Document:
Rev.1
Page15