Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Random Row Read (Interleaving Banks)
Figure 12.1
(Burst Length = 8, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK1
High
CS
RAS
CAS
WE
DSF
BS
RAy
RAy
RAx
RAx
A9
RBx
A0 ~ A8
CAy
CAx
RBx CBx
tRCD
tWR
tRP
DQM
DQ
Hi-Z
DBx7
DAy0
Write
DAx5DAx6
DBx2 DBx3
DBx6
DAy2
DAy3
DAy1
DAx0
DAx4
DAx3
DBx1
DBx5
DBx4
DAx2
DAx7
DAx1
DBx0
Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Command
Bank A
Activate
Command
Write
Write
Command
Bank A
Command
Bank B
Bank A
Document:
Rev.1
Page22
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
