Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 10.1
Random Column Write (Page within same Bank)
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK1
CS
RAS
CAS
WE
DSF
BS
RBw
A9
RBz
A0 ~ A8
RBw
CBx
CBw
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2
DBy2
DBy3
DBx0
DBy1
DBw3
DBx1 DBy0
Write
DBz0
DBz2 DBz3
DBz1
Activate
Write
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank B
Command
Bank B
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Document:
Rev.1
Page16