VIS
Description
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing
268,435,456 bits. The 256Mb DDR SDRAM is internally configured as a quad bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed oper-
ation. The double data rate architecture is essentially a 2n prefetch architecture with an inter-
face designed to transfer two data words per clock cycle at the I/O pins. A single read or write
access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command. which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE com-
mand are used to select the bank and row to be accessed (BA0,BA1 select the bank; A0-A11
select the row). The address bits registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. the following sections pro-
vide detailed information covering device initialization, register definition, command descrip-
tions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. Power must first be applied to
V
DD
, then to V
DDQ
, and finally to V
REF
(and to the system V
TT
). V
TT
must be applied after V
DDQ
to avoid device latch-up, which may cause permanent damage to the device. V
REF
can be applied
any time after V
DDQ
, but is expected to be nominally coincident with V
TT
. Except for CKE, inputs
are not recognized as valid until after V
REF
is applied. CKE is an SSTL_2 input, but will detect an
LVCMOS LOW level after V
DD
is applied. Maintaining an LVCMOS LOW level on CKE during
power-up will put the DQ and DQS outputs in the High-Z stage, where they will remain until driven
in normal operation (by a read access). After all power supply and reference voltages are stable,
and the clock is stable, the DDR SDRAM requires a 200
µ
s delay prior to applying an executable
a command.
Once the 200
µ
s delay has been satisfied, a COMMAND INHIBIT or NOP comand should be
applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL
command should be applied. Next a LOAD MODE REGISTER command should be issued for the
Extended Mode Register to enable the DLL, then a LOAD MODE REGISTER comand should be
issued for the base mode Register, to reset the DLL, and to program the operating parameters.
200 clock cycles are required between the DLL reset and any read command. A PRECHARGE
ALL command should be applied, placing the device in the “all banks idle” stage.
Document : 1G5-0157
Rev.1
Page 8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
