Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
FUNCTIONAL BLOCK DIAGRAM- X4 CONFIGURATION
CKE
CLK#
CLK
Generator
CS#
LOGIC
BANK3
BANK2
BANK1
WE#
CAS#
RAS#
CLK
REFRESH
COUNTER
13
MODE REGISTERS
13
ROW-
BANK0
ROW-
ADDRESS
LATCH
&
BANK0
MEMORY
ARRAY
(8192x1024x8)
13
ADDRESS
DATA
DLL
MUX
8192
13
4
4
DECODER
8
SENSE AMPLIFIERS
READ
LATCH
MUX
4
DRVRS
DQS
GENERATOR
8
1
DO0
DQ3,DM
2
COL0
INPUT
REGISTERS
1
I/O GATING
BANK0
CONTROL
LOGIC
DM MASK LOGIC
DQS
DOS
1
1
4
2
MASK
2
1
A0-A12
BA0-BA1
1
4
WRITE
FIFO
&
ADDRESS
RESGISTER
15
8
(x8)
RCVRS
DRIVERS
8
COLUMN
DECODER
4
ctk
in
ctk
out
4
4
DATA
10
1
COLUMN
ADDRESS
COUNTER/
LATCH
11
CLK
COL0
COL0
1
Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the
device; it does not necessarily represent an actual circuit implementation.
Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional
DQ and DQS signals.
Document : 1G5-0157
Rev.1
Page4
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
