Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
FUNCTIONAL BLOCK DIAGRAM- X16 CONFIGURATION
CKE
CLK#
CLK
Generator
CS#
LOGIC
BANK3
BANK2
BANK1
WE#
CAS#
RAS#
CLK
REFRESH
COUNTER
13
MODE REGISTERS
13
ROW-
BANK0
ROW-
ADDRESS
LATCH
&
BANK0
MEMORY
ARRAY
13
ADDRESS
MUX
DATA
DLL
8192
(8192x256x32)
13
16
16
DECODER
32
SENSE AMPLIFIERS
READ
LATCH
MUX
16
DRVRS
DQS
GENERATOR
32
1
DO0-
DQ15,L
UDM
2
COL0
INPUT
REGISTERS
1
I/O GATING
BANK0
CONTROL
LOGIC
DM MASK LOGIC
LDQS,
UDQS
DQS
1
1
2
MASK
2
1
A0-A12
BA0-BA1
1
WRITE
FIFO
&
ADDRESS
RESGISTER
15
32
(x32)
RCVRS
16
16
16
DRIVERS
32
COLUMN
DECODER
16
ctk
in
ctk
out
16
DATA
8
COLUMN
ADDRESS
COUNTER/
LATCH
9
CLK
COL0
COL0
1
1
Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the
device; it does not necessarily represent an actual circuit implementation.
Note 2: LDM and VDM are unidirectional signal (input only) but is internally loaded to match the load of the
bidirectional DQ and DQS signals.
Document : 1G5-0157
Rev.1
Page6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
