Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
Table 1
BURST DEFINITION
Burst Length
Starting Column
Address:
Order of Accesses Within a Burst
A0
2
0
1
0-1
1-0
0-1
1-0
A1-A0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
0 1
1 0
1 1
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1
0
1
0
1
8
1
0
1
1
NOTE:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data-element block; A0-A2 selects the first access within the block.
4.Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the
block.
Document : 1G5-0157
Rev.1
Page11
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
