VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
9.3 WRITE to READ Command Interval
The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data pre-
ceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior
to the first DOUT
.
WRITE to READ Command Interval
Burst lengh=4
T7
T0
T1
T3
T6
T8
T2
T4
T5
CLK
1 cycle
Command
Read B
WRITE A
CAS latency=2
Hi-Z
DA0
QB0
QB1
QB2
QB3
DQ
Command
Write A
DA0
Read B
CAS latency=3
DQ
Hi-Z
QB0
QB1
QB3
QB2
9.4 READ to WRITE Command Interval
During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance
using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command.
This restriction is necessary to avoid a data bus conflict.
Document:1G5-0189
Rev.1
Page22
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
