VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During a READ cycle, the BURST READ operation can be terminated by a PRECHARGE
command. When the PRECHARGE command is asserted, the BURST READ operation is termi-
nated and PRECHARGE starts.
Read data will remain valid until zero clock(CAS latency of 1), one clock(CAS latency of 2)or
two clocks(CAS latency of 3) after the PRECHARGE command and the same bank can be acti-
vated again after tRP(min) from the PRECHARGE command.
PRECHARGE TERMINATION in READ Cycle
Burst lengh= X
T8
T7
T0
T1
T3
T6
T2
T4
T5
CLK
ACT
Read
Read
Read
PRE
Command
tRP
CAS latency=1
DQ
Hi-Z
Q0
Q3
Q2
Q1
tRP
PRE
Q2
ACT
Command
CAS latency=2
DQ
Hi-Z
Q0
Q3
tRP
Q1
command
ACT
PRE
tRP
CAS latency=3
DQ
Hi-Z
Q0
Q3
Q2
Q1
Document:1G5-0189
Rev.1
Page25
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
