VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
7.PRECHARGE
The PRECHARGE command can be asserted anytime after tRAS(min) is satisfied.
Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM
enters the idle state after tRP(min) is satisfied. The parameter tRP is the time required to perform the PRECHARGE.
The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the
burst is as followed.
PRECHARGE
Burst lengh=4
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Command
Read
PRE
CAS latency=2
DQ
Hi-Z
Q1
Q0
Q2
Q3
Command
CAS latency=3
DQ
PRE
Read
Hi-Z
Q0
Q1
Q3
Q2
CAS latency=
(tRAS is satisfied)
2: One clock earlier than the last output data.
3: Two clocks earlier than the last output data.
In order to write all data to the memory cell correctly, the asynchronous parameter”tDPL” must be satisfied.
The tDPL(MIN.) specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE
cycle. The minimum number of clocks are calculated by dividing tDPL(min.) by the clock cycle time.
In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid
data. In the following table, minus means clocks before the reference, plus means time after the reference.
CAS latency
2
READ
-1
WRITE
+tDPL(min.)
3
-2
+tDPL(min)
Document:1G5-0189
Rev.1
Page18
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
