VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
10.BURST TERMINATION
There are two methods to terminate a BURST operation other than using a READ or a WRITE command.
One is the BURST STOP command and the other is the PRECHARGE command.
10.1 BURST STOP Command
During a READ BURST. when the BURST STOP command is asserted, the BURST READ outputs
are terminated and the data bus goes to high-impedance after the CAS latency from the BURST STOP
command.
During a WRITE BURST. when the BURST STOP command is asserted, any data provided at that
cycle will not be written. The BURST WRITE is effectively terminated and no further data can be written
until a new WRITE command is asserted.
Burst Termination
Burst lengh=X, CAS Intency=2,3
T7
T0
T1
T3
T6
T2
T4
T5
CLK
BST
Read
Command
Hi-Z
CAS latency=1
DQ
Q0
Q1
Q0
Q2
Hi-Z
CAS latency=2
DQ
Q1
Q0
Q2
Q1
Hi-Z
CAS latency=3
DQ
Q2
Remark BST: Burst stop command
Burst lengh=X, CAS latency=1,2,3
T7
T0
T1
T3
T6
T2
T4
T5
CLK
BST
Write
Q0
Command
CAS latency=1,2,3
DQ
Hi-Z_
Q0
Q1
Q2
Remark BST: Burst stop command
Document:1G5-0189
Rev.1
Page24
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
