VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
8.2 WRITE with AUTO PRECHARGE
During a WRITA cycle, the AUTO PRECHARGE starts at tDPL(min.) after the last data word input to
the device
WRITE with AUTO PRECHRGE
Burst lengh=4
T0
T1
T3
T6
T8
T2
T4
T5
T7
CLK
Command
WRITA B
AUTO PRECHARGE starts
tDPL
CAS latency=2
DQ
Hi-Z_
DB0
DB1
DB2
DB3
Command
WRITA B
AUTO PRECHARGE starts
tDPL
CAS latency=3
DQ
Hi-Z_
DB0
DB1
DB2
DB3
Remark WRITA means WRITE with AUTO PRECHARGE
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is
valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency
2
READ
-1
WRITE
+tDPL(min.)
3
-2
+tDPL(min)
Document:1G5-0189
Rev.1
Page20
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
