VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
8.AUTO PRECHARGE
During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is
high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRE-
CHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst
access.
In the WRITE cycle, tDAL(min.) must be satisfied to assert the next active command to the bank being pre-
charged.
When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important
because the tRAS must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can
be asserted after tRP(min.) has been satisfied.
The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed
into the mode register and on whether the cycle is READ or WRITE.
8.1 READ with AUTO PRECHARGE
During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two
clocks earlier(CAS Iatency of 3) than the last data word output.
READ with AUTO PRECHARGE
Burst lengh=4
T7
T8
T0
T1
T3
T6
T2
T4
T5
CLK
Command
READA B
Auto precharge starts
CAS latency=2
DQ
Hi-Z
QB0
QB1
QB2
QB3
Command
READA B
Auto precharge starts
CAS latency=3
DQ
Hi-Z
QB0
QB0
QB1
QB1
QB2
QB3
Remark: READA means READ with AUTO PRECHARGE
Document:1G5-0189
Rev.1
Page19
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
