VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
9.READ/WRITE Command Interval
9.1 READ to READ command interval
When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency,
even if the previous READ operation has not completed. READ will be interrupted by another READ.
A READ command can be asserted in every clock without restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T6
T0
T1
T3
T2
T4
T5
T7
T8
CLK
Read B
Read A
Command
Hi-Z_
DQ
QA0
QB0
QB1
QB2
QB3
1 cycle
9.2 WRITE to WRITE Command Interval
When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated
and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE.
A WRITE command can be asserted in every clock without restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T6
T2
T4
T5
T7
T8
CLK
Write B
Write A
Command
Hi-Z_
DQ
QA0
QB0
QB1
QB2
QB3
1 cycle
Document:1G5-0189
Rev.1
Page21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
