VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
10.2.2 PRECHARGE TERMINATION in WRITE Cycle
During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE
command. when the PRECHARGE command is asserted, the BURST WRITE operation in imme-
diately terminated and PRECHARGE starts.
The same bank can be activated again after tRP(min.) from the PRECHARGE command. The
DQM must be high to mask invalid data in.
When CAS latency is 1, 2 or 3, the data written prior to the PRECHARGE command will be
correctly stored. However, invalid data may be written at the same clock as the PRECHARGE
command. To prevent this from happening, DQM must be high at the same clock as the PRE-
CHARGE command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
T8
T7
T0
T1
T3
T6
T2
T4
T5
CLK
PRE
ACT
Write
Command
tRP
CAS latency=1
DQM
Hi-Z
DQ
D0
D3
D2
D4
D1
tRP
Write
PRE
ACT
Command
CAS latency=2
DQM
Hi-Z
DQ
D0
D3
D2
D4
D1
tRP
command
Write
PRE
ACT
CAS latency=3
DQM
Hi-Z
DQ
D0
D3
D2
D4
D1
Document:1G5-0189
Rev.1
Page26