VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
6.Address Bits of Bank-Select and Precharge
0
1
Row A0 A1 A2
(Activate command)
A3 A4
Select Bank A ”Activate” command
Select Bank B ”Activate” command
A6 A7
A5
A8 A9 A10
A11
A11
Row A0 A1 A2
(Precharge)
A3 A4
A6 A7
A10
A5
A8 A9
Result
A11
0
A10
0
Precharge Bank A
Precharge Bank B
Precharge All Banks
1
x
0
1
x:Don’t care
0
1
Disable Auto-Precharge (End of Burst)
Enable Auto-Precharge (End of Burst)
Col. A0 A1 A2
(CAS strobes)
A3 A4
A6 A7
A10
A11
A5
A8 A9
Enable Read/Write commands for Bank A
Enable Read/Write commands for Bank B
0
1
Document:1G5-0189
Rev.1
Page17
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
