G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116.
Table 1.2. Hardware Signal Definitions (5 of 8) (Cont.)
Pin Label
RSPDAT [1..2]
Buffer Type Signal Name
Description
Receive Side
Special Purpose
Port Data
TTL-O-TS-65 Data output for special purpose port. RSPDAT changes on
programmable edge of RSPCLK.
TXCLK [A..D]+/-
Transmit Side
Drop Clock
LVDS-I
Clock reference for the STS-48/192 incoming transmit flow carried in
TXDAT[A..D][15..0] in 155 MHz mode, or TXDAT[A..D][3..0] in 622 MHz
mode
The clock frequency is nominally 155.52 MHz equivalent to STS-48/192
/STM-16/64 operation in 155 MHz rate mode.
The clock frequency is nominally 622.08 MHz equivalent to STS-48/192
/STM-16/64 operation in 622 MHz rate mode.
TXFP [A..D]+/-
Transmit Side
Drop Frame
Pulse
LVDS-I
In 155 MHz rate mode: Frame references for the STS-48/192 / STM-
16/64 incoming transmit flows carried in TXDAT[A..D][15..0]. The frame
pulse must have low-to-high transitions coincident with the first framing
byte, A1 #1 of the STS-48/192 / STM-16/64 frames (optionally first byte
following last Z0 byte). When TXFP is used in 155 MHz mode, the first
A1 byte must be aligned to TXDAT[n][15..8].
In both multiplex modes, TXFP[n] is a frame reference for
TXDAT[n][15..0], and TXFP[n] is sampled on the rising edge of
TXCLK[n]+, where n = {A,B,C,D}, i.e. in STS-192/STM-64 mode, all four
frame references need to be applied and active at the same time.
In 622 MHz rate mode: Frame references for the STS-48/192 / STM-
16/64 incoming transmit flows carried in TXDAT[A..D][3..0]. The frame
pulse must have low-to-high transitions coincident with the first framing
bytes most significant nibble, A1 #1 of the STS-48/192 / STM-16/64
frames (optionally first byte most significant nibble following last Z0
byte).
In both multiplex modes, TXFP[n] is a frame reference for
TXDAT[n][3..0], and TXFP[n] is sampled on the rising edge of
TXCLK[n]+, where n = {A,B,C,D}, i.e. in STS-192/STM-64 mode, all four
frame references need to be applied and active at the same time.
TXCLKOUT [A..D]+/-
Transmit Side
Drop Clock
Source
LVDS-O
LVDS-O
Clock source for the transmit direction of the drop side STS-48/192
transmit interfaces. One clock is provided for each of the four STS-48
interfaces. The clock frequency can be configured to 155.52 MHz or
622.08 MHz.
The clock is squelched for approximately 800 ns during asynchronous
assertion of TXRST. The clock is not squelched when the drop interface
operates in 622 MHz.
TXSYNC_TXRST [A..D]+/- Transmit Side
Synchronization
STS-48/192 / STM-16/64 outgoing synchronization signal, operating in
either frame pulse mode or reset mode.
(Outgoing)/Trans
mit Side Reset
(Outgoing)
In frame pulse mode, this pin reflects the required frame position in time
of the data at TXDAT and TXFP. The signal is 8 kHz, 50% duty cycle.
The positive edge indicates the frame pulse position.
In reset mode, the pin resets the transmit flow of the device sourcing
TXDAT and TXFP, hence determining the position in time of the
frames. The signal is programmable active low or high. The signal is
asserted for approximately 400 ns.
TXPRTY [A..D]+/-
Transmit Side
Drop Parity
LVDS-I
Parity (even/odd) over the incoming transmit STS-48/192 / STM-16/64
data stream.
In 155 MHz rate mode: TXPRTY[n] is the parity over TXDAT[n][15..0]
(optionally including TXFP[n]), where n = {A,B,C,D}. TXPRTY[A..D] is
sampled on the rising edge of TXCLK[A..D]+.
In 622 MHz rate mode: TXPRTY[n] is the parity over TXDAT[n][3..0]
(optionally including TXFP[n]), where n = {A,B,C,D}. TXPRTY[A..D] is
sampled on the rising edge of TXCLK[A..D]+.
1.0 Product Description
Page 31.
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
