G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116.
Table¬1.2. Hardware Signal Definitions (1 of 8)
Pin Label
CLKRSTEN
Buffer Type Signal Name
TTL-I-ST-PD Clock Reset
Enable
Description
When asserted, all flip-flops used in programmable reference clock
(TXRCLK, RXRCLK) circuitry will be reset during Power-Up Reset.
Hence the programmable reference clock outputs will halt during power
up reset.
When de-asserted, these flip-flops will not be reset and the
programmable reference clock outputs will be toggling during power-up
reset.
The signal is a schmitt-triggered input with an internal pull-down
resistor.
RSTTXPLLB
RSTRXPLLB
TTL-I-ST-PU Transmit Side Pll The internal PLL in the transmit side is asynchronously reset while this
Reset
signal is asserted (low). Independent reset of the PLL may not be
required since the PLL is also reset by Power Up Reset. If not used,
this signal must be tied high.
The signal is a schmitt-triggered input with an internal pull-up resistor.
TTL-I-ST-PU Receive Side Pll The internal PLL in the receive side is asynchronously reset while this
Reset
signal is asserted (low). Independent reset of the PLL may not be
required since the PLL is also reset by Power Up Reset. If not used,
this signal must be tied high.
The signal is a schmitt-triggered input with an internal pull-up resistor.
TXRCLK
TTL-O-50
TTL-O-50
Transmit Side
Reference clock derived from TLCLK by a programmable divider circuit.
Reference Clock The divider can be programmed in the range 2kHz to 78 MHz.
Receive Side Reference clock derived from RLCLK by a programmable divider circuit.
Reference Clock The divider can be programmed in the range 2 kHz to 78 MHz.
RXRCLK
RSTPOWUPB
TTL-I-ST-PU Power Up Reset The entire device is asynchronously reset while this signal is asserted
(low). The only flip-flops not reset are the ones used in clock dividers
and high-speed data paths. Flip-flops used for programmable reference
clock generation may or may not be reset (see CLKRSTEN pin).
The signal is a schmitt-triggered input with an internal pull-up resistor.
RSTB
TTL-I-ST-PU Device Master
Reset
Asynchronous reset of the device. The entire device excluding clock
generating circuit (dividers and PLLs) is held in a reset state while the
RSTB signal is asserted (low). All configuration bits except the ones
used for clock generation are reset to their reset values.
The signal is a schmitt-triggered input with an internal pull-up resistor.
CSB
ALE
TTL-I
TTL-I
CPU Chip Select Must always be asserted during register read/write access cycles. The
CSB signal (active low) is used in conjunction with either the RDB or
the WRB signal.
CPU Address
Latch Enable
Controls internal latching of the address bus signals. On transition from
high to low the address bus A[8..0] is latched internally. When high the
internal address bus latches are transparent. This signal will allow for
interfacing to a multiplexed address/data bus. If not used, it must be
tied high.
RDB
TTL-I
TTL-I
CPU Read
Enable
Used for register read operations. Active low. D[7..0] will drive the
register content of the register selected by A[8..0] when RDB and CSB
are both asserted.
Used for register write operations. Active low. D[7..0] content is written
into the register selected by A[8..0] on WRB transition from low to high
when CSB is asserted.
WRB
CPU Write
Enable
1.0 Product Description
Page 27.
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
