G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116
Table 1.2. Hardware Signal Definitions (4 of 8) (Cont.)
Pin Label
RLCLK+/-
Buffer Type Signal Name
Description
Receive Side
Line Clock
LVDS-I
LVDS-I
LVDS-I
Clock reference for the 10Gb/s receive flow carried in RLIN[15..0]. The
clock frequency is nominally 622.08 MHz equivalent to STS-192/STM-
64 operation.
Parallel data bus for the incoming STS-192/STM-64 data stream.
RLIN[15] is the most significant bit, and first arriving bit on the serial
data stream. RLIN[15..0] is sampled on the rising edge of RLCLK+.
Frame pulse for the receive line interface. RLFP can be used instead of
the internal framing circuit (based on A1A2 pattern) for synchronizing
the receive processor. RLFP must have a low-to-high transition
coincident with the first A1 byte or the first payload byte
RLIN [15..0]+/-
RLFP+/-
Receive Side
Line Data
Receive Side
Line Frame Pulse
(programmable). The pulse must be at least one cycle wide. When
RLFP is used, the first A1 byte of the SONET/SDH trace must be
aligned to RLIN[15..8]. RLFP is sampled on the rising edge of RLCLK+.
RLPRTY+/-
LOF
Receive Side
Line Parity
LVDS-I
Parity input (even/odd parity) for the receive line data RLIN[15..0]
(optionally including RLFP). RLPRTY is sampled on the rising edge of
RLCLK+.
Status signal indicating if Loss Of Frame (LOF) has been detected. The
LOF status is also available in an internal status register bit. The signal
is active high.
Status signal indicating if Loss Of Signal (LOS) has been detected. The
LOS status is also available in an internal status register bit. The signal
is active high.
LOPC is monitored and changes in the signal status may cause
generation of an interrupt and HW consequent actions. This allows
monitoring of optical failures via the device CPU interface. When LOPC
is asserted, the receive processor is optionally clocked by the transmit
clock (derived from TLCLK). The active level of this signal is
programmable. The signal is schmitt-triggered.
Receive Side
Loss Of Frame
TTL-O-50
TTL-O-50
TTL-I-ST
LOS
Receive Side
Loss Of Signal
LOPC
Receive Side
Loss of Optical
Carrier
RTOHCLK
RTOHFP
Receive Side
Transport
Overhead Port
Clock
Receive Side
Transport
Overhead Port
Frame Pulse
TTL-O-TS-50 Clock reference for the receive transport overhead port. The clock
frequency is 77.76 MHz.
TTL-O-TS-65 Frame reference for the receive transport overhead port. RTOHFP is a
one clock cycle wide pulse coincident with the first framing byte, A1 #1,
being transmitted on RTOH[7..0]. RTOHFP changes on programmable
edge of RTOHCLK.
RTOHVALID
RTOH [7..0]
Receive Side
Transport
Overhead Port
Valid
Receive Side
Transport
Overhead Port
Data
TTL-O-TS-65 Valid qualifier for the receive transport overhead port. RTOHVALID is
asserted (programmable level) when there is valid data on RTOH[7..0].
RTOHVALID changes on programmable edge of RTOHCLK. Between
each row of overhead RTOHVALID will be de-asserted.
TTL-O-TS-65 Data output for the receive transport overhead (section/regenerator and
line/multiplex) bytes extracted from the incoming STS-192/STM-64
signal. RTOH[7..0] changes on programmable edge of RTOHCLK.
RSPCLK [1..2]
RSPFP
Receive Side
Special Purpose
Port Clock
Receive Side
Special Purpose
Port Frame Pulse
TTL-O-TS-65 Clock reference for receive special purpose output port. The clock is a
2.16 MHz, 50% duty-cycle signal (optionally gapped to match the
bandwidth of RSPDAT.
TTL-O-TS-65 Frame reference for special purpose output ports RSPDAT[1..2]. The
frame pulse is a one clock cycle wide pulse coincident with the first bit
of the serial data streams. Active high. RSPFP changes on
programmable edge of RSPCLK[1..2].
RSPVALID [1..2]
Receive Side
Special Purpose
Port Valid
TTL-O-TS-65 RSPVALID is asserted (programmable level) when there is valid data
on RSPDAT. RSPVALID changes on programmable edge of RSPCLK.
Page 30
1.0 Product Description
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
