G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116.
Table 1.2. Hardware Signal Definitions (7 of 8) (Cont.)
Pin Label
Buffer Type Signal Name
Description
TLOUT [15..0]+/-
Transmit Side
Line Data
LVDS-O
Parallel data bus for the outgoing STS-192/STM-64 data stream.
TLOUT[15] is the most significant bit, and the first transmitted bit on the
serial data stream. TLOUT[15..0] is generated on the rising edge of the
outgoing TLCLKOUT+.
TLPRTY+/-
TLCLK+/-
Transmit Side
Line Parity
LVDS-O
LVDS-I
Parity output (even/odd parity) for the transmit line data TLOUT[15..0]
(optionally including TLFP). TLPRTY is generated on the rising edge of
the outgoing TLCLKOUT+.
Incoming clock reference for the 10 Gb/s transmit flow carried in
TLOUT[15..0]. The clock frequency is configurable to either nominally
155.52 MHz or 622.08 MHz determined by the SELTLCLKRATE input
signal.
Transmit Side
Line Reference
Clock
SELTLCLKRATE
TLSYNCLVDS+/-
Select Transmit TTL-I-PU
Side Line
Reference Clock
Rate
Controls the clock rate/frequency of the incoming clock reference
(TLCLK+/-) for the 10 Gb/s transmit flow carried in TLOUT[15..0].
’Low’: TLCLK+/- is operating at 155 MHz
’High’: TLCLK+/- is operating at 622 MHz
Transmit Side
Synchronization
Pulse (Incoming)
LVDS Level
LVDS-I
LVDS version of the incoming transmit synchronization signal.
Specifies the phase in generation of frames in the Tx flow. It is an 8 kHz
cyclic signal, the positive edge indicates the required frame position in
time.
The signal must be asserted for minimum two TLCLK clock cycles
when TLCLK is 155 MHz and minimum eight TLCLK clock cycles when
TLCLK is 622 MHz. The signal can operate with either a synchronous
or an asynchronous AC timing reference to TLCLK. In asynchronous
mode the minimum pulse width must be extended with at least one
more TLCLK cycle.
TLSYNCTTL
Transmit Side
Synchronization
Pulse (Incoming)
TTL Level
TTL-I-PD
TTL version of the incoming transmit synchronization signal.
Specifies the phase in generation of frames in the Tx flow. It is an 8 kHz
cyclic signal, the positive edge indicates the required frame position in
time.
The signal must be asserted for minimum three TLCLK clock cycles
when TLCLK is 155 MHz and minimum nine TLCLK clock cycles when
TLCLK is 622 MHz. The signal operates with an asynchronous AC
timing reference to TLCLK.
INTTXFP
DROPFP
Internal Transmit TTL-O-65
Side Frame Pulse
An 8 kHz signal with a positive pulse width of one 77.76 MHz clock
period. The positive edge reflects the internal transmit frame phase and
may be use for diagnostic purposes.
One out of the four (selectable via CPU) available frame pulses
reflecting the frame phase of the four incoming STS-48/STM-16 signals
at the drop interface. The signal is an 8KHz signal with a positive pulse
width of one 77.76 MHz clock period.
Selected Drop
Frame Pulse
TTL-O-65
(Transmit Side)
Optimum phase alignment at the drop interface is obtained when
DROPFP rising edge and INTTXFP rising edge are co-incident. The
signal may be use for diagnostic purposes.
DROPLOF
Selected Drop
Loss Of Frame
(Transmit Side)
TTL-O-65
The associated loss of frame status of the selected drop frame pulse
signal DROPFP.
1.0 Product Description
Page 33.
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
