G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116
Table 1.2. Hardware Signal Definitions (2 of 8) (Cont.)
Pin Label
Buffer Type Signal Name
Description
A [8..0]
CPU Address
TTL-I
Address bus selects specific internal registers during register read/write
access.
D [7..0]
INTB
CPU Data
TTL-IO-20
Bi-directional data bus is used to transfer data for microprocessor
read/write access to internal device registers.
TTL-O-OD-20 Asserted (i.e. driven low) when an internal interrupt source is pending
and the interrupt is unmasked (enabled). The signal is de-asserted (i.e.
open) when the interrupt pending bits have been cleared.
The signal is an open drain signal.
CPU Interrupt
PMTICK
Performance
Monitoring Tick
TTL-IO-20
The signal can be configured as an output or an input.
Configured as output: Asserted when the internal PMTICK timer
generates a tick for latching performance counters in the device.
Configured as input: A low-to-high transition will (optionally) latch
performance monitoring counters in the device.
GPIO [7..0]
TMS
General Purpose TTL-IO-50
Input/Output
Individually configurable as inputs or outputs. When configured as
inputs, they can trigger an interrupt.
Intended for controlling/monitoring external devices.
Controls the test operations that are carried out using the IEEE P1149.1
test access port. When asserted (low), the internal JTAG circuitry is
functional. When de-asserted, the device operates normally.
The signal is sampled on the rising edge of TCK and has an internal
pull-up resistor.
JTAG Test Mode TTL-I-PU
Select
TRSTB
JTAG Test Reset TTL-I-ST-PU Provides an asynchronous test access port reset via the IEEE P1149.1
test access port. When asserted (low), the JTAG test access port
circuitry is reset to a predefined state.
The signal is a schmitt triggered input with an internal pull-up resistor.
TCK
TDI
JTAG Test Clock TTL-I
This signal provides timing for test operations that are carried out using
the IEEE P1149.1 test access port. Max frequency is 1 MHz.
This signal carries test data into the device via the IEEE P1149.1 test
access port. TDI is sampled on the rising edge of TCK. TDI has an
internal pull-up resistor.
JTAG Test Data TTL-I-PU
Input
TDO
JTAG Test Data TTL-O-TS-65 This signal carries test data out of the device via the IEEE P1149.1 test
Output
access port. TDO is updated on the falling edge of TCK. The TDO
signal is a tristate output, which is inactive except when data scan
shifting is in progress.
RXCLK155 [A..D]+/-
RXCLK622 [A..D]+/-
RXPRTY [A..D]+/-
Receive Side
Drop Clock: 155
MHz mode
Receive Side
Drop Clock: 622
MHz mode
LVDS-O
LVDS-O
LVDS-O
Clock reference for the STS-48/192 outgoing receive flow carried in
RXDAT[A..D][15..0]. The clock frequency is nominally 155.52 MHz
equivalent to STS-48/192 /STM-16/64 operation.
Clock reference for the STS-48/192 outgoing receive flow carried in
RXDAT[A..D][15:12]. The clock frequency is nominally 622.08 MHz
equivalent to STS-48/192 /STM-16/64 operation.
Receive Side
Drop Parity
Parity (even/odd) over the outgoing receive STS-48/192 / STM-16/64
data stream
In 155 MHz rate mode: RXPRTY[n] is the parity over RXDAT[n][15..0]
(optionally including RXFP[n]), where n = {A,B,C,D}. RXPRTY[A..D]
changes on the rising edge of RXCLK155[A..D]+.
In 622 MHz rate mode: RXPRTY[n] is the parity over RXDAT[n][15..12]
(optionally including RXFP[n]), where n = {A,B,C,D}. RXPRTY[A..D]
changes on the rising edge of RXCLK622[A..D]+.
Page 28
1.0 Product Description
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
