G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116
Table 1.2. Hardware Signal Definitions (6 of 8) (Cont.)
Pin Label
Buffer Type Signal Name
Description
TXDAT [A..D][15..0]+/-
Transmit Side
Drop Data
LVDS-I
STS-48/192 / STM-16/64 incoming Transmit side drop Data. The
interface operates either at 155 MHz or 622 MHz utilizing a shared pin
scheme.
In 155 MHz rate mode: When no cross connect is performed (default).
In STS-48/STM-16 multiplex mode , TXDAT[A][15..0] carries STS-
48/STM-16 #1, TXDAT[B][15..0] carries STS-48/STM-16 #2,
TXDAT[C][15..0] carries STS-48/STM-16 #3, and TXDAT[D][15..0]
carries STS-48/STM-16 #4. TXDAT[n][15] is the most significant bit.
In STS-192/STM-64 mode, TXDAT[A..D][15..0] carries the STS-
192/STM-64 data stream, i.e. TXDAT[A..D][15..0] is interpreted as one
64 bit bus. TXDAT[A][15] is the most significant bit, and TXDAT[D][0]
the least significant bit.
In both multiplex modes each TXDAT[n][15..0] is sampled on the rising
edge of TXCLK[n]+, where n = {A,B,C,D}, i.e. one clock signal for each
16 bits group.
In 622 MHz rate mode: When no cross connect is performed (default).
In STS-48/STM-16 multiplex mode , TXDAT[A][3..0] carries STS-
48/STM-16 #1, TXDAT[B][3..0] carries STS-48/STM-16 #2,
TXDAT[C][3..0] carries STS-48/STM-16 #3, and TXDAT[D][3..0] carries
STS-48/STM-16 #4. TXDAT[n][3] is the most significant bit.
In STS-192/STM-64 mode, TXDAT[A..D][3..0] carries the STS-
192/STM-64 data stream, i.e. TXDAT[A..D][3..0] is interpreted as one
16 bit bus. TXDAT[A][3] is the most significant bit, and TXDAT[D][0] the
least significant bit.
In both multiplex modes each TXDAT[n][3..0] is sampled on the rising
edge of TXCLK[n]+, where n = {A,B,C,D}, i.e. one clock signal for each
4 bits group.
TISPCLK
TISPFP
Transmit Side
Internal Section
Port Clock
Transmit Side
Internal Section
Port Frame Pulse
TTL-O-TS-65 Clock reference for internal section port in the transmit side. The clock
is a 2.16 MHz, 50% duty-cycle signal (optionally gapped to match the
bandwidth of TISPDAT.
TTL-O-TS-65 Frame reference for internal section port in the transmit side. The frame
pulse is a one clock cycle wide pulse coincident with the first bit of the
serial data streams. Active high. TISPFP changes on a programmable
edge of TISPCLK.
TISPVALID
Transmit Side
Internal Section
Port Valid
TTL-O-TS-65 Valid qualifier for the internal section port in the transmit side.
TISPVALID is asserted (programmable level) when there is valid data
on TISPDAT. TISPVALID changes on a programmable edge of
TISPCLK.
TISPDAT
Transmit Side
Internal Section
Port Data
TTL-O-TS-65 Data output for internal section port in the transmit side. TISPDAT
changes on a programmable edge of TISPCLK.
TLCLKOUT+/-
Transmit Side
Line Clock
LVDS-O
LVDS-O
LVDS-O
Outgoing STS-192/STM-64 transmit clock for the line interface.
TLCLKOUT is generated internally from TLCLK by a PLL. The clock
frequency is nominally 622.08 MHz equivalent to STS-192/STM-64
operation.
Outgoing STS-192/STM-64 divided transmit clock for the line interface.
TLCLKOUTDIV is generated internally by dividing TLCLKOUT. The
clock frequency is nominally 155.52 MHz (divide by 4) or 77.76 MHz
(divide by 8). The signal is generated on the rising edge of TLCLKOUT.
TLCLKOUTDIV+/-
TLFP+/-
Transmit Side
Line Clock
Divided
Transmit Side
Line Frame Pulse
A one clock cycle wide pulse coincident with either the first framing byte
(A1 #1), or the first payload byte. TLFP is generated on the rising edge
of the outgoing TLCLKOUT+.
Page 32
1.0 Product Description
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
