G56047-0, Rev 1.1
STS-192/STM-64 SONET/SDH Transceiver
VSC9116.
Table 1.2. Hardware Signal Definitions (3 of 8) (Cont.)
Pin Label
RXFP [A..D]+/-
Buffer Type Signal Name
Description
Receive Side
Drop Frame
Pulse
LVDS-O
In 155 MHz rate mode: Frame reference for the STS-48/192 / STM-
16/64 outgoing receive flows carried in RXDAT[A..D][15..0]. The frame
pulse(s) is a one clock cycle pulse programmable to be coincident with
any byte pair in the first row of the Section overhead or the first payload
byte pair of the STS-48/192 / STM-16/64 frames. RXFP[A..D] changes
on the rising edge of RXCLK155[A..D]+.
In 622 MHz rate mode: Frame reference for the STS-48/192 / STM-
16/64 outgoing receive flows carried in RXDAT[A..D][15..12]. The frame
pulse(s) is a one clock cycle pulse programmable to be coincident with
the most significant nibble of any of the bytes in the first row of the
Section overhead or the first payload byte of the STS-48/192 / STM-
16/64 frames.
RXFP[A..D] changes on the rising edge of RXCLK622[A..D]+.
RXDAT [A..D][15..0]+/-
Receive Side
Drop Data
LVDS-O
In 155 MHz rate mode:
If no cross connect is performed (default).
In STS-48/STM-16 multiplex mode RXDAT[A][15..0] carries STS-
48/STM-16 #1, RXDAT[B][15..0] carries STS-48/STM-16 #2,
RXDAT[C][15..0] carries STS-48/STM-16 #3, and RXDAT[D][15..0]
carries STS-48/STM-16 #4. RXDAT[n][15] is the most significant bit,
where n = {A,B,C,D}.
In STS-192/STM-64 multiplex mode RXDAT[A..D][15..0] carries the
STS-192/STM-64 data stream, i.e. RXDAT[A..D][15..0] is interpreted as
one 64 bit bus. RXDAT[A][15] is the most significant bit, and
RXDAT[D][0] the least significant bit. RXDAT[A..D][15..0] changes on
the rising edge of RXCLK155[A..D]+.
In the 622 MHz rate mode:
If no cross connect is performed (default).
In STS-48/STM-16 multiplex mode RXDAT[A][15..12] carries STS-
48/STM-16 #1, RXDAT[B][15..12] carries STS-48/STM-16 #2,
RXDAT[C][15..12] carries STS-48/STM-16 #3, and RXDAT[D][15..12]
carries STS-48/STM-16 #4. RXDAT[n][15] is the most significant bit,
where n = {A,B,C,D}.
In STS-192/STM-64 multiplex mode RXDAT[A..D][15..12] carries the
STS-192/STM-64 data stream, i.e. RXDAT[A..D][15..12] is interpreted
as one 16 bit bus. RXDAT[A][15] is the most significant bit, and
RXDAT[D][12] the least significant bit. RXDAT[A..D][15:12] changes on
the rising edge of RXCLK622[A..D]+.
RISPCLK
RISPFP
Receive Side
Internal Section
Port Clock
Receive Side
Internal Section
Port Frame Pulse
TTL-O-TS-65 The clock is a 2.16 MHz, 50% duty-cycle signal (optionally gapped to
match the bandwidth of RISPDAT).
TTL-O-TS-65 This signal is a one clock cycle wide pulse indicating the start of a new
data stream on RISPDAT. When RISPFP is asserted, the first bit of
RISPDAT is sampled on RISPCLK between 1 and 4.5 clock cycles
later, depending on the programming of clocking edge and latency.
RISPREN
RISPDAT
Receive Side
Internal Section
Port Read Enable
TTL-O-TS-65 Signal for enabling data at RISPDAT. The response latency (from
RISPREN is asserted until RISPDAT is sampled) is programmable. The
edge of RISPCLK on which this signal is output is programmable. This
signal is not used in gapped RISPCLK mode.
Receive Side
Internal Section
Port Data
TTL-I
Data input for receive internal section port. The signal is sampled on
either the rising or the falling edge (programmable) of RISPCLK.
1.0 Product Description
Page 29.
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
