VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
4.6 Receiver Operation
The functional timing diagram for the receive side is shown below. If a synch word is received, the signals
RXTYP[1:0] will be set to 00. If data is received, these bits will be set to 01, 10, or 11. If IDLE words are received,
the signal RXWA will go LOW.
Figure 16: Direct Mode Receiver Functional Timing
WCLK
RXIN[31:0]
RXTYP[1:0]
MSG D0 D1
1, 2, or 3
D2 D3 D4 D5
D0
D1 D2 D3
DN
0
RXWA
Receiving IDLEs
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Page 32
G52190-0, Rev 4.1
01/05/01
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