VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
words, are passed through the switch matrix. In this case, command words such as IDLEs must be used periodically
for checking the link integrity. At the last word of a cell clock period, if the user sends an IDLE word, bits B[1:0] of
the IDLE word are set to ‘11’ to embed the cell clock information. The switch will flag a cell sync error if this IDLE
word does not contain a cell clock. The transmitter can force an IDLE word at the end of any given cell period by
setting the signal TXEN LOW.
Figure 11: Cell Mode Transmitter Functional Timing at Port Card
WCLK
User defined cell period
TXIN[31:0]
TXTYP[1:0]
RTM/TCLK
D1 D2
D3 D4 D5 D6
D0
D1
D0
D2 D3 D4
DN
1 or 2 or 3
3.4 Receiver Operation
At the receiving side, the transceiver examines incoming words and overhead bits. Figure 12 shows the receiver
timing diagram. If the received words are data, the overhead bits RXTYP[1:0] will be set to 01, 10 or 11. If the
received word is a command word, RXTYP[1:0] will be set to 00. If the received word is an IDLE word, the signal
RXWA will also go LOW. If the transceiver receives an IDLE word during the last word of the cell clock period
without B[1:0] = 11, a cell sync error condition will be flagged, and the signal TXOK will pulse HIGH.
Figure 12: Cell Mode Receiver Functional Timing at Port Card
WCLK
User defined cell period
RXIN[31:0]
RXTYP[1:0]
D0
D1 D2
D3 D4 D5 D6
D0
D1
DN
D2 D3 D4
1 or 2 or 3
RCLK
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Page 28
G52190-0, Rev 4.1
01/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
