VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
their reference clock inputs from the same source and use their internal CMU as the transmit bit clock. In this case the
LTIME signal is set LOW. The transceivers on the port card use the recovered bit clock as the source of the transmit
bit clock, so LTIME must be set HIGH. The table in section 1.5 summarizes these modes of operation.
4.4 Link Initialization
Link initialization is completed at power up or at user request. Word alignment is done automatically on both
transmit and receive data links. Either the transmit or receive side can be word aligned independently of each other.
Either side can create a transmit clock from its local CMU source or from the clock recovered from the received serial
data stream. The MODE[1] signal enables transmitter word alignment when it is set HIGH. The MODE[0] signal
enables receiver word alignment when it is set HIGH. For any given serial connection, only one of these signals on
each end of the link should be set HIGH.
For the case of using the transceiver in a simple port to port switching system, only the receiver word aligner is
enabled. The initialization sequence is as described in section 1.1 except that both transceivers start sending ALIGN
words at power up. In this configuration, without the switch to act as the master in the initialization process, the
receiver has to align to both the ALIGN words and the IDLE words for its word boundary.
For the case of using the transceivers in the backplane interconnect link, all transceivers on the switch card are
used in master clock mode where they generate both the transmit and receive word boundary which the port cards
align to. In this case, MODE[1:0] are set LOW for transceivers on the switch card. These transceivers are
synchronized to a master REFCLK. Since each transceiver is word aligned to the REFCLK, they are all synchronized
to the same word boundary and the same clock frequency at the switch fabric interface. Transceivers at the port cards
perform word alignment on both the transmit and receive side so MODE[1:0] are set HIGH. The link initialization
process is similar to the case of transceiver to the switch synchronization as described earlier in section 1.1.4.
4.5 Transmitter Operation
The functional timing diagram for the transmit side is shown below. Synch words be inserted into the data by
setting TXTYP[1:0] = 00. This initiates the data scrambling sequence in the transceiver. Normal data words should be
loaded into the transceiver with these bits set to 01, 10, or 11. If no data is ready to be transmitted at the parallel
interface, TXEN should be set LOW and the transceiver will send out IDLE words.
Figure 15: Direct Mode Transmitter Functional Timing
WCLK
TXIN[31:0]
TXTYP[1:0]
TXEN
SYN D0 D1
1, 2, or 3
D2 D3 D4 D5
D0
D1 D2 D3
DN
0
Set low if no data is ready
Needed to initiate the scrambling pattern
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52190-0, Rev 4.1
01/05/01
Page 31
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
