VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
Figure 18: Receive Data Output Timing Diagram
WCLK
TDEL1
RXOUT[31:0], RXTYP[1:0],
RXWA, RXOK, TXOK, ACK/RCLK
RFM, REN,RTM/TCLK
TSKEW
TDEL2
WSIN
Table 3: Receive Data Output Timing Table
Parameter
Description
Min
Typ
Max
Units
WCLK to RXOUT[31:0], RXTYP[1:0], RXWA, ACK/
RCLK, RXOK, TXOK, OOS delay
TDEL1
TDEL1
TDEL2
0.0
0.7
2.0
4.5
7.0
9.0
ns
ns
ns
WCLK to RFM, REN, RTM/TCLK delay
WSIN to RXOUT[31:0], RXTYP[1:0], RXOK, TXOK,
OOS delay
TDEL2
TDEL2
TSKEW
TDEL
WSIN to RFM, REN, RTM delay
WSIN to RXWA, ACK/RCLK
2.5
1.5
11.5
7.5
1.5
5.5
3.0
ns
ns
ns
ns
ns
Output data skew with respect to WCLK
WCLK to TCLK delay
0.5
TSKEW
WCLK to WCLK skew using parallel transceivers
Table 4: Misc. Timing Parameters
Parameter
Description
Min
Typ
Max
Units
TLT
CMU and CRU lock time
Word synchronization time
100
30
us
us
TWS
(# words
in cell)2
TCS
Cell synchronization time per transceiver
WCLKs
TPM
TCM
Data latency in packet mode with zero serial trace delay
Data latency in cell mode with zero serial trace delay
Data latency in direct mode with zero serial trace delay
CRQ to REN delay time with zero serial trace delay
Reference (word) clock period
8
12
6
WCLKs
WCLKs
WCLKs
WCLKs
ns
TDM
TCRQ
8
TREFCLK
FREFCLK
JREFCLK
16
Reference clock frequency stability
50
7
ppm
Reference clock input jitter
ps RMS
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 34
G52190-0, Rev 4.1
01/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
