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VSC870TX 参数 Datasheet PDF下载

VSC870TX图片预览
型号: VSC870TX
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能串行背板收发器 [High Performance Serial Backplane Transceiver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 40 页 / 512 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE  
SEMICONDUCTOR CORPORATION  
Data Sheet  
High Performance Serial  
Backplane Transceiver  
VSC870  
Figure 14: Back Plane Interconnect Using VSC870 Transceivers  
Port Card  
Memory  
System  
Trans  
Trans  
VSC870  
Parallel  
VSC870  
Switch  
Fabric  
Port Card  
Memory  
System  
Trans  
Trans  
VSC870  
VSC870  
4.2 Data Encoding Format  
When the BYPASS signal is HIGH, the RXTYP[1:0] and TXTYP[1:0] signals are the direct representation of the  
overhead bits (B[1:0]) in the serial channels. For data words, the user can use these bits for signaling to the receiving  
port card. Information such as start of frame and end of frame can be passed with the data in this manner. Scrambling  
must be used in all cases. At the serial interface, the data words are scrambled to increase the signal edge transition  
density by setting the SCRAM input HIGH. When scrambling is enabled, a command word must be used to initialize  
the scrambling sequence. The transceiver checks for bit patterns on IDLE words to detect a link error condition. The  
encoding for the data at the parallel interface and the two overhead bits at the serial interface are described in the  
following table. The format for data words and command words is described in section 1.2.  
TXTYP[1:0]RX  
TYP[1:0]  
Direct Mode  
CELLSYN = 0  
B[1:0]  
SCRAM = 1  
SCRAM = 0  
Error Check  
0 0  
0 1  
1 0  
1 1  
0 0  
0 1  
1 0  
1 1  
Command Word  
Data Word  
No Scramble  
Scramble  
Scramble  
Scramble  
No Scramble  
No Scramble  
No Scramble  
No Scramble  
IDLE words  
No  
No  
No  
Data Word  
Data Word  
4.3 Loop Timing  
Loop timing depends on the source of the transmitters bit clock. For the case of using the transceiver in a simple  
port to port switching system, one transceiver can act as the master and one as the slave. The master will have LTIME  
set LOW so that its CMU will generate the bit timing. The slave will have LTIME set HIGH so that its transmitter  
uses the bit clock recovered from its clock recovery unit, therefore the whole system is in a single clock domain.  
For the case of using the transceivers as a backplane interconnect link, all transceivers on the switch card have  
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012  
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  
Page 30  
G52190-0, Rev 4.1  
01/05/01  
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