VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
AC Characteristics
Table 1: LVDS and TTL Outputs
Parameters
Description
Min
Typ
Max
Units
Conditions
TR,TTL
TF,TTL
TR,LVDS
TF,LVDS
TTL Output Rise Time
TTL Output Fall Time
LVDS Output Rise Time
LVDS Output Fall Time
2.5
2.5
ns
ns
ps
ps
10-90% @ 50pF
10-90% @ 50pF
20-80%
100
100
20-80%
Figure 17: Transmit Data Input Timing Diagram
TWCLK
WCLK
TDEL
TINH1
TINSU1
TXIN[31:0], TXTYP[1:0],
DLYEN/CCKIN, TXEN, ABORT RTR
TINH2
TINSU2
WSIN
TWSOUT
Table 2: Transmit Data Input Timing Table
Parameter
Description
Min
Typ
Max
Units
TWCLK
TINSU1
TINSU1
TINSU1
TINSU1
TINH1
Word clock period
16.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
TXIN[31:0] setup time with respect to WCLK
TXTYP[1:0] setup time with respect to WCLK
TXEN setup time with respect to WCLK
ABORT, RTR setup time with respect to WCLK
Data hold time with respect to WCLK
5.5
6.0
7.0
8.5
0.0
TWSOUT
TINSU2
TINSU2
Word Synch Output clock period
16.0
TXIN[31:0] setup time with respect to WSIN
TXTYP[1:0] setup time with respect to WSIN
2.0
2.0
DLYEN/CCKIN, TXEN setup time with respect to
WSIN
TINSU2
2.5
ns
TINSU2
TINH2
TDEL
ABORT, RTR setup time with respect to WSIN
Data hold time with respect to WSIN
Delay time from WSIN to WCLK
4.5
2.0
1.6
ns
ns
ns
5.5
NOTE: Duty cycle for WCLK and WSOUT is 50% +/- 10% worst case.
During initialization, the WSOUT minimum pulse width can be reduced by an additional 1nS.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52190-0, Rev 4.1
01/05/01
Page 33
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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