VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
3.0 Cell Mode
3.1 Overview
In Cell Mode, a more sophisticated arbitration scheme can be supported by using the VSC870 and the VSC880 in
conjunction with a user defined queuing logic on the port cards and a scheduling device on the switch card. To
activate this mode, the signal BYPASS is set HIGH and the signal CELLSYN is set HIGH. In this mode, only fixed
length data packets (cells) can be supported. The central scheduling chip can control the switch using the parallel
configuration interface of the switch chip. Messages containing port card queue information are sent to the
scheduling chip using an out-of-band control bus. The scheduler performs arbitration and routing based on these
messages. Results of the arbitration and flow control are then sent back as messages to the port cards using the out-of-
band control bus (see the VSC880 data sheet for more information). Multiple transceivers and switch chips can be
used in parallel to achieve higher bandwidth (see Application Note 32: Design Guide for a Cell Based Switch with
Central Control).
If multiple transceivers are used on a port card, RTR should be set LOW. In this case, the switch and the
transceiver provide a cell synchronous switching fabric for data transfer between port cards and the scheduler chip.
Transaction between ports, switch and scheduler are synchronized to a master cell clock. This cell clock, which is
also used by the scheduler chip, is connected to the switch chip or to multiple switch chips. The switch chip
distributes the cell clock to all connected transceivers during link initialization. The transceivers at the port cards
adjust their transmit cell clocks so that all transceivers send the first word of a cell at such time that it arrives at the
switch chip aligned to the switch chip cell clock. On the receiving side, all transceivers adjust their receiving pipeline
in order to match the delay from their transmitting cell clock to their receiving cell clock by a predetermined number
of word clocks. In this way, parallel transceivers can align receiving data to a common cell clock boundary. The word
clock delay number depends on the distance from the transceivers to the switch and can be adjusted by using
command words as described in 1.2.3. In this mode, the BYPASS signal and CELLSYN signal in the transceiver and
the CMODE signal on the switch chip must be set HIGH. By setting the BYPASS signal HIGH, all logic in the
transceiver used for the self-routing capability in Packet Mode is disabled. A picture of a cell based system is shown
below.
If a single transceiver is used on a port card, set RTR HIGH. In this case, the master cell clock sent from the
switch chip to the transceivers is embedded in the serial data. This cell clock is recovered by the transceiver during
initialization. The transmit cell clock is generated from this recovered cell clock and phase shifted so that the
transmitted cell boundary is aligned with the cell clock at the switch.This recovered cell clock can be used to clock
other slave transceivers as in the case RTR=LOW. In this case, the transceiver does not perform pipeline stage
adjustment as in the case of RTR=LOW.
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VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
