VSC8601 Datasheet
Configuration
Table 32.
Auxiliary Control and Status, Address 28 (0x1C) (continued)
Bit
8
Name
Access Description
Default
D polarity inversion
Reserved
RO
RO
RO
1 = Polarity swap on pair D.
0
7:6
5
FDX status
1 = Full duplex.
0 = Half duplex.
0
4:3
Speed status
RO
00 = Speed is 10BASE-T.
01 = Speed is 100BASE-TX.
10 = Speed is 1000BASE-T.
11 = Reserved.
00
2
1
Reserved
RO
Sticky Reset Enable
R/W
This is a super-sticky bit.
1 = Enabled. When enabled, all MII
register bits listed as sticky retain
their values during a software
reset.
1
0 = Disabled. When disabled, all
MII register bits listed as sticky
change to their default values
during a software reset.
Note that bits listed as super sticky
retain their values during a
software reset regardless of this
setting.
0
Reserved
RO
4.2.26
Delay Skew Status
The following table lists the settings available.
Delay Skew Status, Address = 29 (0x1D)
Table 33.
Bit
15
Name
Access Description
Default
000
Reserved
RO
14:12
11
Pair A delay skew
Reserved
RO
RO
RO
RO
RO
RO
RO
Skew in integral symbol times
10:8
7
Pair B delay skew
Reserved
Skew in integral symbol times
Skew in integral symbol times
Skew in integral symbol times
000
6:4
3
Pair C delay skew
Reserved
000
2:0
Pair D delay skew
000
4.2.27
Reserved Address Space
The bits in register 30 (0x1E) are reserved.
Revision 4.1
September 2009
Page 54
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
