VSC8601 Datasheet
Configuration
Table 38.
Enhanced LED Behavior, Address 17E (0x11) (continued)
Bit
Name
Access Description
Default
1
LED1 combine
feature disable
R/W
This is a sticky bit.
0 = Combine enabled (Link/Activity,
Duplex/Collision).
0
1 = Disable Combination (Link only, Duplex
only).
0
LED0 combine
feature disable
R/W
This is a sticky bit.
0 = Combine enabled (Link/Activity,
Duplex/Collision).
0
1 = Disable Combination (Link only, Duplex
only).
Note Bit 4 must be set to 1 before register 16E and 17E are enabled for enhanced
LED control. If set to 0, then the LED features in 16E and 17E are not relevant. If set to
1, then the LED features in register 27 are not relevant.
4.3.4
CRC Good Counter
Register 31E makes it possible to read the contents of the CRC good counter; the
number of CRC routines that have executed successfully. The following table lists the
possible readouts.
Table 39.
CRC Good Counter, Address 18E (0x12)
Bit
Name
Access Description
Default
15
Packet since last
read
RO
This is a self-clearing bit.
1 = Packet received since last read.
0
14
Reserved
RO
RO
13:0 CRC good counter
contents
This is a self-clearing bit.
0x000
Counter containing the number of packets
with valid CRCs. This counter does not stop
counting and will roll over.
4.3.5
MAC Resistor Calibration Control
The following table lists the settings available.
Table 40.
MAC Resistor Calibration Control, Address 19E (0x13)
Bit
15:14 MAC resistor
calibration control
Name
Access Description
Default
R/W
RO
This is a sticky bit.
CMODE
00 = 50 Ω.
01 = 60 Ω.
10 = 30 Ω.
11 = 45 Ω.
setting
13:0
Reserved
Revision 4.1
September 2009
Page 58
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