VSC8115
Data Sheet
PLL Bypass Operation
The BYPASS pin is intended for use in production test and should be set at logic LOW in the normal operation. If
both BYPASS and STS12 pins are set at logic HIGH, the VSC8115 will bypass the PLL and present an inverted
version of the REFCLK to the clock output CLKOUT±. The REFCLK’s rising edge is used to capture data at
DATAIN± and transmit data at DATAOUT±. This bypass operation can be used to facilitate the board debugging
process.
DATAIN±
2
2
DATAOUT±
PLL Clock
(on-chip)
REFCLK
STS12
BYPASS
0
1
2
CLKOUT±
LOCKREFN
SD
LOS
(on-chip)
Figure 1. Control Diagram for Signal Detection and PLL Bypass Operation
Table 1. Signal Detect and PLL Bypass Operation Control
STS12
1
1
1
1
1
0
0
0
0
0
BYPASS
0
0
0
0
1
0
0
0
0
1
LOCKREFN
1
1
0
0
X
1
1
0
0
X
SD
1
0
1
0
X
1
0
1
0
X
DATAOUT
DATAIN
LOW
LOW
LOW
DATAIN
DATAIN
LOW
LOW
LOW
Not Allowed
CLKOUT
PLL Clock
PLL Clock
PLL Clock
PLL Clock
REFCLK
PLL Clock
PLL Clock
PLL Clock
PLL Clock
Not Allowed
3 of 12
G52272, Rev 4.2
5/14/03
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
