VSC8115
Data Sheet
F
UNCTIONAL
D
ESCRIPTION
The VSC8115 contains an on-chip Phase Locked-Loop (PLL) consisting of a phase/frequency detector (PFD), a loop
filter using one external capacitor, a LC-based voltage-controlled oscillator (VCO), and a programmable frequency
divider. The PFD compares the phase relationship between the VCO output and an external 19.44MHz LVTTL
reference clock to make coarse adjustments to the VCO block so that its output is held within ±500ppm of the
reference clock. The use of reference clock minimizes the PLL lock time during power up and provides a stable
output clock source in the absence of serial input data. The PFD also compares the phase relationship between the
VCO output and the serial data input to make fine adjustments to the VCO block. The loop filter converts the phase
detector output into a smooth DC voltage. This DC voltage is used as the input to the VCO block whose output
frequency is a function of the input voltage. The VCO output signal is fed into a programmable frequency divider that
generates either a 622.08Mb/s signal if STS12 is HIGH, or a 155.52Mb/s signal if STS12 is LOW, back to the PFD.
Lock Detection
The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to indicate that
the PLL is locked to the serial data inputs and that valid data and clock are present at the high-speed differential
outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or the VCO has
drifted away from the local reference clock by more than 500ppm.
LOCKDET requires that the reference clock be present to operate properly.
Signal Detection
The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a LVPECL
input and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate an LOS condition and
are connected inside the part as shown in
Figure 1 on page 3.
If either one of these two inputs goes LOW and
BYPASS is LOW, the VSC8115 will enter a Loss of Signal (LOS) state, and will hold the DATAOUT± output at logic
LOW state. During the LOS state, the VSC8115 will also hold the output clock CLKOUT± to within ±500ppm of the
REFCLK. See
Table 1 on page 3.
Most optical modules have an SD output. This SD output indicates that there is sufficient optical power and is
typically active HIGH. If the SD output on the optical module is LVPECL, it should be connected directly to the SD
input on the VSC8115, and the LOCKREFN input be tied HIGH. If the SD output is LVTTL, it should be connected
directly to the LOCKREFN input, and the SD input should be tied HIGH.
The SD and LOCKREFN inputs also can be used for other applications when it is required to hold the CLKOUT±
output to within ±500ppm of the reference clock and to force the DATAOUT± output to the logic LOW state.
Reference Clock
Upon powering up the VSC8115, it is recommended that the reference clock be present at least 40 bit times before the
data signal is introduced.
2 of 12
G52272, Rev 4.2
5/14/03
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
