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VSC8115YA-03 参数 Datasheet PDF下载

VSC8115YA-03图片预览
型号: VSC8115YA-03
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, TSSOP-20]
分类和应用: ATM异步传输模式电信光电二极管电信集成电路
文件页数/大小: 12 页 / 549 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC8115  
Data Sheet  
High-Speed Outputs  
The high-speed output buffers, DATAOUT and CLKOUT , can be terminated as either LVDS or LVPECL outputs.  
If used as LVDS outputs, the transmission lines should be routed with 100 differential impedance and need to be  
terminated at the receive end with a 100 resistor across the differential pair. If used as LVPECL outputs the  
transmission line should be 50 terminated, with 50 pull-down resistors near the receiving end. See Figure 4 and  
Figure 5.  
VSC8115  
100  
Figure 4. High-Speed Outputs—LVDS Termination  
DC-Coupled  
VDD -2.0V  
VSC8115  
Receiver  
R
50  
1
R
50  
2
VDD -2.0V  
Creates 2V bias  
when VDD = 3.3V  
AC-Coupled  
VDD  
Receiver  
(unbiased with no  
internal termination)  
VSC8115  
R
82  
1
CIN  
VDD  
R
124  
R
168  
2
5
R
82  
3
CIN  
VSS  
R
124  
R
168  
4
6
VSS  
Receiver  
VSC8115  
CIN  
(biased with  
internal termination)  
R
168  
1
CIN  
R
168  
2
Figure 5. High-Speed Outputs—LVPECL Terminations  
8 of 12  
G52272, Rev 4.2  
5/14/03  
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